A method and system of ensuring coherency of a sequence of instructions to be executed by a processor having a trace unit and an execution unit includes grouping at least a portion of the sequence of instructions to form at least one trace where a status of the at least one trace is set to a verified status when the at least one trace is formed; holding in the at least one trace a coherency component that includes a pointer to a physical address of the at least one trace; receiving, based on the coherency component, the pointer to the physical address as associated with an invalidating event, and in response thereto, setting the status of the at least one trace to be an unverified status; and preventing the at least one trace from being executed when the status of the at least one trace is the unverified status.