A method is provided to incorporate information currently known about an integrated circuit's design, including peripheral components that share the same printed circuit board (PCB) with the integrated circuit, to automate a clock signal instantiation and routing solution to realize a comprehensive design. The information derived from a hardware design synthesis tool includes the existence of PCB resources, such as fixed-frequency oscillators, that may co-exist with a particular integrated circuit, such as a programmable logic device (PLD). Other derived information includes details concerning clock modules and cores that may exist within the PLD in accordance with the PLD's design specification. Once the information that describes the PLD and its environment is known, the information is utilized to automatically instantiate resource interconnect cores and automatically generate connections between the fixed-frequency oscillators, resource interconnect cores, and PLD implemented cores that are contained within the design.