A computer system comprises host processor and a network interface, wherein the host processor includes resources supporting a full power mode, a lower power mode and a power down mode, as seen in standard system bus specifications such as PCI and InfiniBand. The network interface includes a medium interface unit coupled to network media supporting a least high speed protocol, such as a Gigabit Ethernet or high-speed InfiniBand, and a lower speed protocol, such as one of 10 Mb and 100 Mb Ethernet or a lower speed InfiniBand. Power management circuitry forces the medium interface unit to the lower speed protocol in response to an event signaling entry of the lower power mode. In the lower power mode, the network interface consumes less than the specified power when executing the lower speed protocol, and consumes greater than the specified power when executing the high speed protocol. Logic in the network interface operates in the lower power mode, and uses the lower speed protocol to detect a pattern in incoming packets. In response to the detection of said pattern, the logic issues a reset signal to the host processor. Thus, the network interface operates as a wake-up device in the lower power mode, using the lower speed protocol.