Invention Grant
US08049330B2 Wafer-level chip scale packaging for LED comprising carrier substrate with thermally conductive through holes and fill channels
有权
用于LED的晶片级芯片级封装包括具有导热通孔和填充通道的载体衬底
- Patent Title: Wafer-level chip scale packaging for LED comprising carrier substrate with thermally conductive through holes and fill channels
- Patent Title (中): 用于LED的晶片级芯片级封装包括具有导热通孔和填充通道的载体衬底
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Application No.: US11284936Application Date: 2005-11-23
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Publication No.: US08049330B2Publication Date: 2011-11-01
- Inventor: Ra-Min Tain , Wei-Chung Lo , Li-Cheng Shen
- Applicant: Ra-Min Tain , Wei-Chung Lo , Li-Cheng Shen
- Applicant Address: TW Hsin-Chu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsin-Chu
- Agency: Stout, Uxa, Buyan & Mullins, LLP
- Priority: TW94119688A 20050614; TW94133223A 20050923
- Main IPC: H01L23/36
- IPC: H01L23/36 ; H01L23/373
Abstract:
A structure of light emitting diode (LED) wafer-level chip scale packaging (WL-CSP) is disclosed. The process of making the same is also provided in this invention. The LED CSP utilizes the through hole metal filling to enhance heat conduction between the LED die and its carrier substrate. The CSP structure is achieved by bonding pre-processed through-hole-filling carrier substrate against the flip-chip LED wafer.
Public/Granted literature
- US20060278885A1 LED wafer-level chip scale packaging Public/Granted day:2006-12-14
Information query
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