发明授权
US08054859B2 Precesion/speed compromise of a synchronization signal reception device
有权
同步信号接收装置的预处理/速度泄漏
- 专利标题: Precesion/speed compromise of a synchronization signal reception device
- 专利标题(中): 同步信号接收装置的预处理/速度泄漏
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申请号: US12452051申请日: 2008-06-06
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公开(公告)号: US08054859B2公开(公告)日: 2011-11-08
- 发明人: Serge Defrance , Thierry Tapie , Ingrid Autier
- 申请人: Serge Defrance , Thierry Tapie , Ingrid Autier
- 申请人地址: FR Boulogne-Billancourt
- 专利权人: Thomson Licensing
- 当前专利权人: Thomson Licensing
- 当前专利权人地址: FR Boulogne-Billancourt
- 代理商 Robert D. Shedd; Harvey D. Fried; James McKenzie
- 优先权: FR0755689 20070612
- 国际申请: PCT/EP2008/057097 WO 20080606
- 国际公布: WO2008/151998 WO 20081218
- 主分类号: H04J3/06
- IPC分类号: H04J3/06
摘要:
A reception device is able to receive packets in a communication network comprising at least two stations. The device is capable of receiving packets containing samples of the network which originate from data sampled every period Tsmp, where Tsmp emanates from a time base synchronized on all the stations of the said network; regenerating a counting ramp with the aid of a loop receiving the samples and furthermore delivering local samples every period Tsmp and a clock. The phase-locked loop comprises: a samples comparator comparing the samples and the local samples and delivering an error signal; a corrector receiving the signal and delivering a corrected error signal, the corrector having a static gain equal to 1; a digital oscillator receiving the corrected error signal and delivering the clock, which has a frequency dependent on the signal and is proportional to a gain. According to the invention, the phase-locked loop comprises, furthermore, a gain adjustment device which determines a gain value as a function of the error signal.
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