发明授权
US08059650B2 Hardware based parallel processing cores with multiple threads and multiple pipeline stages
有权
基于硬件的并行处理核心，具有多个线程和多个流水线阶段
- 专利标题： Hardware based parallel processing cores with multiple threads and multiple pipeline stages
- 专利标题（中）： 基于硬件的并行处理核心，具有多个线程和多个流水线阶段
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申请号： US11932656申请日： 2007-10-31
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公开(公告)号： US08059650B2公开(公告)日： 2011-11-15
- 发明人: Suhas A. Shetty , De B. Vu
- 申请人： Suhas A. Shetty , De B. Vu
- 申请人地址： US CA Sunnyvale
- 专利权人： Aruba Networks, Inc.
- 当前专利权人： Aruba Networks, Inc.
- 当前专利权人地址： US CA Sunnyvale
- 代理机构： Blakely, Sokoloff, Taylor & Zafman
- 主分类号： H04L12/28
- IPC分类号： H04L12/28
摘要：
A pipelined out-of-order process and system for handling data packets in a network device. The process and system are scalable to support throughput in excess of 10 Gbps. The system includes a set of processing cores that offload the table look up operations and similar operations from the central processing unit. The central processing unit receives the requisite data needed for performing forwarding, routing, NAT, firewall maintenance and similar operation on data packets from the set of processing cores.
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