A data driver includes a shift register circuit configured to receive a first clock signal, a second clock signal, and a start signal, and to sequentially provide a sampling signal, a conversion circuit configured to receive the first clock signal, the second clock signal, and the sampling signal, and to sequentially provide a conversion signal, a sampling latch circuit configured to store data according to the sampling signal and the conversion signal, and a holding latch circuit configured to receive the data from the sampling latch circuit in response to first and second enable signals, and to provide a first data signal or a second data signal to data lines corresponding to the received data.