A device having temperature evaluating capabilities, the device includes: (i) a temperature sensitive delay line that comprises multiple first type NMOS transistors and first type PMOS transistors; (ii) an configurable delay line that comprises second type NMOS transistors and second type PMOS transistors; wherein a process condition sensitivity of first type NMOS transistors and first type PMOS transistors substantially equals a process condition sensitivity of the second type NMOS transistors and second type PMOS transistors; wherein the configurable delay line is less sensitive to temperature than the temperature sensitive delay line; (iii) a phase detector, coupled to an output of the temperature sensitive delay line and to an output of the adjustable delay line, the phase detector is adapted to determine a difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the adjustable delay line; and (iv) a controller, adapted to: (a) find a configuration of the configurable delay line that introduces a delay that substantially equals a delay introduced by the temperature sensitive delay line; and (b) determine a temperature of the temperature sensitive delay line in response to the found configuration.