Invention Grant
- Patent Title: Transceiver with latency alignment circuitry
- Patent Title (中): 具有延迟对准电路的收发器
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Application No.: US11465230Application Date: 2006-08-17
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Publication No.: US08086812B2Publication Date: 2011-12-27
- Inventor: Kevin Donnelly , Mark Johnson , Chanh Tran , John B. Dillon
- Applicant: Kevin Donnelly , Mark Johnson , Chanh Tran , John B. Dillon , Nancy D. Dillon, legal representative
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Vierra Magen Marcus & DeNiro LLP
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.
Public/Granted literature
- US20070011426A1 TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY Public/Granted day:2007-01-11
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