发明授权
US08086916B2 System and method for running test and redundancy analysis in parallel 有权
并行运行测试和冗余分析的系统和方法

System and method for running test and redundancy analysis in parallel
摘要:
A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different types of fails, and each of the testing portions performs multiple tests on the memory locations and outputs fail information for at least a part of the memory device. The queue stores the fail information. The redundancy analyzer processes the fails using the fail information and produces a plurality of repair solutions. The types of fails include must fails and sparse fails. The fail information is transmitted to the queue, and the fail information includes at least a part of the fail information for the entire memory device. The tester can operate asynchronously from the redundancy analyzer.
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