An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.