发明授权
- 专利标题： Stress memorization dielectric optimized for NMOS and PMOS
- 专利标题（中）： 针对NMOS和PMOS优化的应力记忆电介质
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申请号： US12541335申请日： 2009-08-14
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公开(公告)号： US08101476B2公开(公告)日： 2012-01-24
- 发明人: Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
- 申请人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238
摘要：
A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not through NMOS source and drain anneal. A SiN dielectric layer is deposited such that an area ratio of a Si—H peak to a N—H peak in a FTIR spectrum is greater than 7 and a tensile stress of the SiN dielectric is greater than 150 MPa. The CMOS integrated circuit is annealed after deposition of the SiN dielectric layer and the SiN dielectric layer is removed from at least a part of the integrated circuit.
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