A method and apparatus for clock recovery in synchronous digital systems. The apparatus includes a phase frequency detector, a loop filter, a compressor, and a clock generator. The phase frequency detector generates a phase error signal based on a difference between an input clock signal and an output clock signal. The loop filter multiplies the phase error signal and filters the multiplied phase error signal. The compressor divides the loop filter output. Based on the compressor output, the clock generator generates an output clock signal is provided as a feedback signal to the phase error detector. The apparatus may also include a glitch cleaner for deglitching the input clock signal.