Invention Grant
- Patent Title: Peak power detection in digital designs using emulation systems
- Patent Title (中): 使用仿真系统的数字设计中的峰值功率检测
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Application No.: US12346004Application Date: 2008-12-30
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Publication No.: US08108194B2Publication Date: 2012-01-31
- Inventor: Bing Zhu , Tsair-Chin Lin , Tung-sun Tung , Jingbo Gao
- Applicant: Bing Zhu , Tsair-Chin Lin , Tung-sun Tung , Jingbo Gao
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining power-activity values for the one or more segments; determining power-consumption values for the one or more segments from the power-activity values; using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in the one or more time windows; and saving one or more values for power activity of the DUT in a computer-readable medium.
Public/Granted literature
- US20090271167A1 PEAK POWER DETECTION IN DIGITAL DESIGNS USING EMULATION SYSTEMS Public/Granted day:2009-10-29
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