Invention Grant
- Patent Title: Method for fabrication of a semiconductor device and structure
- Patent Title (中): 半导体器件和结构的制造方法
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Application No.: US12797493Application Date: 2010-06-09
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Publication No.: US08115511B2Publication Date: 2012-02-14
- Inventor: Zvi Or-Bach
- Applicant: Zvi Or-Bach
- Applicant Address: US CA San Jose
- Assignee: MonolithIC 3D Inc.
- Current Assignee: MonolithIC 3D Inc.
- Current Assignee Address: US CA San Jose
- Agency: Venable LLP
- Agent Michael A. Sartori
- Main IPC: G06F7/38
- IPC: G06F7/38 ; H01L25/00
Abstract:
A configurable integrated circuit (IC) system comprising: a first die comprising input/output cells; and a configurable logic second die connected by a first plurality of through-silicon-vias (TSVs) to the first die.
Public/Granted literature
- US20100259296A1 METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE Public/Granted day:2010-10-14
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