Invention Grant
US08115516B2 Circuit arrangement for filtering unwanted signals from a clock signal, processing system and method of filtering unwanted signals from a clock signal
有权
用于从时钟信号滤波不想要的信号的电路装置，处理系统以及从时钟信号滤除不想要的信号的方法
- Patent Title: Circuit arrangement for filtering unwanted signals from a clock signal, processing system and method of filtering unwanted signals from a clock signal
- Patent Title (中): 用于从时钟信号滤波不想要的信号的电路装置，处理系统以及从时钟信号滤除不想要的信号的方法
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Application No.: US12664028Application Date: 2007-06-14
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Publication No.: US08115516B2Publication Date: 2012-02-14
- Inventor: Hubert Bode , Andreas Laudenbach , Andreas Roth , Engelbert Wittich
- Applicant: Hubert Bode , Andreas Laudenbach , Andreas Roth , Engelbert Wittich
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- International Application: PCT/IB2007/052255 WO 20070614
- International Announcement: WO2008/152456 WO 20081218
- Main IPC: G01R29/02
- IPC: G01R29/02
Abstract:
A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement.
Public/Granted literature
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