发明授权
US08117513B2 Test method and test program of semiconductor logic circuit device
失效
半导体逻辑电路器件的测试方法和测试程序
- 专利标题: Test method and test program of semiconductor logic circuit device
- 专利标题(中): 半导体逻辑电路器件的测试方法和测试程序
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申请号: US11887383申请日: 2006-03-27
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公开(公告)号: US08117513B2公开(公告)日: 2012-02-14
- 发明人: Xiaoqing Wen , Seiji Kajihara
- 申请人: Xiaoqing Wen , Seiji Kajihara
- 申请人地址: JP Tokyo
- 专利权人: LPTEX Corporation
- 当前专利权人: LPTEX Corporation
- 当前专利权人地址: JP Tokyo
- 代理机构: McGinn Intellectual Property Law Group, PLLC
- 优先权: JP2005-097015 20050330; JP2005-130806 20050428
- 国际申请: PCT/JP2006/306142 WO 20060327
- 国际公布: WO2006/106626 WO 20061012
- 主分类号: G01R31/28
- IPC分类号: G01R31/28 ; G06F11/00
摘要:
In a combinational portion, when there is one or more unspecified bits in pseudo external input lines and there is no unspecified bit in pseudo external output lines, an assigning operation is carried out. In the combinational portion, when there is one or more unspecified bits in the pseudo external output lines and there is no unspecified bit in the pseudo external input lines, first and second justifying operations are carried out, and a necessary logic value is determined for an unspecified bit of the test cube. In the combinational portion, when there are one more unspecified bits not only in the pseudo external input lines but also the pseudo external output lines, an assigning operation, a justifying operation or first and second assigning/justifying operations are performed upon a focused bit pair.
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