Invention Grant
- Patent Title: Soft error rate mitigation by interconnect structure
- Patent Title (中): 通过互连结构缓解软错误率
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Application No.: US11947832Application Date: 2007-11-30
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Publication No.: US08120175B2Publication Date: 2012-02-21
- Inventor: Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca
- Applicant: Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb I.P. Law Firm, LLC
- Agent Yuanmin Cai, Esq.
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.
Public/Granted literature
- US20090140420A1 SOFT ERROR RATE MITIGATION BY INTERCONNECT STRUCTURE Public/Granted day:2009-06-04
Information query
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