Invention Grant
- Patent Title: Wafer level package having a stress relief spacer and manufacturing method thereof
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Application No.: US12910260Application Date: 2010-10-22
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Publication No.: US08120177B2Publication Date: 2012-02-21
- Inventor: Hyun-Soo Chung , Ho-Jin Lee , Dong-Hyun Jang , Dong-Ho Lee
- Applicant: Hyun-Soo Chung , Ho-Jin Lee , Dong-Hyun Jang , Dong-Ho Lee
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Onello & Mello, LLP
- Priority: KR10-2006-0000786 20060104
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.
Public/Granted literature
- US20110031621A1 WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF Public/Granted day:2011-02-10
Information query
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