发明授权
- 专利标题: Measurement methodology and array structure for statistical stress and test of reliabilty structures
- 专利标题(中): 统计应力的测量方法和阵列结构以及可靠性结构的测试
-
申请号: US12482999申请日: 2009-06-11
-
公开(公告)号: US08120356B2公开(公告)日: 2012-02-21
- 发明人: Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
- 申请人: Kanak B. Agarwal , Nazmul Habib , Jerry D. Hayes , John G. Massey , Alvin W. Strong
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Scully, Scott, Murphy & Presser, P.C.
- 代理商 Anthony J. Canale
- 主分类号: G01V3/00
- IPC分类号: G01V3/00
摘要:
System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.