发明授权
US08121240B1 Statistical measurement of average edge-jitter placement on a clock signal 有权
对时钟信号的平均边缘抖动放置的统计测量

  • 专利标题: Statistical measurement of average edge-jitter placement on a clock signal
  • 专利标题(中): 对时钟信号的平均边缘抖动放置的统计测量
  • 申请号: US10990045
    申请日: 2004-11-16
  • 公开(公告)号: US08121240B1
    公开(公告)日: 2012-02-21
  • 发明人: Ajay Dalvi
  • 申请人: Ajay Dalvi
  • 申请人地址: US CA San Jose
  • 专利权人: Xilinx, Inc.
  • 当前专利权人: Xilinx, Inc.
  • 当前专利权人地址: US CA San Jose
  • 代理商 Scott Hewett; Michael R. Hardaway; LeRoy D. Maunu
  • 主分类号: H04L7/00
  • IPC分类号: H04L7/00 H04L25/00 H04L25/40
Statistical measurement of average edge-jitter placement on a clock signal
摘要:
Phase shift is added between a uttering clock signal and a data bit stream clocked by the clock signal. The phase shift is adjusted until half the data bits are captured (counted) over a measurement period. Adding this amount of phase shift between the clock and data signals centers the average clock edge placement. In a particular embodiment, counters, each having N bits where N is an integer, are used to count clock pulses and data bits. When one counter is full and the most-significant bit on the other counter goes high, the phase shift between the data and clock signal places the average clock edge at the data bit edge.
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