Invention Grant
US08122189B1 Methods for logically combining range representation values in a content addressable memory
有权
在内容可寻址存储器中逻辑地组合范围表示值的方法
- Patent Title: Methods for logically combining range representation values in a content addressable memory
- Patent Title (中): 在内容可寻址存储器中逻辑地组合范围表示值的方法
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Application No.: US12901859Application Date: 2010-10-11
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Publication No.: US08122189B1Publication Date: 2012-02-21
- Inventor: Dinesh Maheshwari
- Applicant: Dinesh Maheshwari
- Applicant Address: US CA Santa Clara
- Assignee: Netlogic Microsystems, Inc.
- Current Assignee: Netlogic Microsystems, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Haverstock & Owens, LLP
- Main IPC: G06F13/00
- IPC: G06F13/00
Abstract:
A method may include comparing a first content addressable memory (“CAM”) entry with a first key value to generate a first comparison result; comparing each of multiple second CAM entries with a second key value to generate multiple second comparison results; and generating a match signal if the first key value matches the first CAM entry and the second key value matches at least one of the multiple second CAM entries.
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