Method of forming bipolar transistor integrated with metal gate CMOS devices

Invention Grant

US08129234B2 Method of forming bipolar transistor integrated with metal gate CMOS devices 失效

Title translation: 与金属栅极CMOS器件集成的双极晶体管的形成方法

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Patent Title: Method of forming bipolar transistor integrated with metal gate CMOS devices
Patent Title (中): 与金属栅极CMOS器件集成的双极晶体管的形成方法
Application No.: US12556205

Application Date: 2009-09-09
Publication No.: US08129234B2

Publication Date: 2012-03-06
Inventor: Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
Applicant: Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
Applicant Address: US NY Armonk
Assignee: International Business Machines Corporation
Current Assignee: International Business Machines Corporation
Current Assignee Address: US NY Armonk
Agency: Scully, Scott, Murphy & Presser, P.C.
Agent H. Daniel Schnurmann
Main IPC: H01L21/8249
IPC: H01L21/8249

Method of forming bipolar transistor integrated with metal gate CMOS devices

Abstract:

A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.

Abstract(Chinese):

形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。通过选择性外延形成的发射体填充台面中的空腔。

Public/Granted literature

US20110057266A1 BIPOLAR TRANSISTOR INTEGRATED WITH METAL GATE CMOS DEVICES Public/Granted day:2011-03-10

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8248	......双极和场效应工艺的结合
H01L21/8249	.......双极和MOS工艺