Invention Grant
- Patent Title: Interfacing between differing voltage level requirements in an integrated circuit system
- Patent Title (中): 集成电路系统中不同电压等级要求之间的接口
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Application No.: US12610276Application Date: 2009-10-31
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Publication No.: US08130030B2Publication Date: 2012-03-06
- Inventor: Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
- Applicant: Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agent Raj Abhyanker, P.C.
- Main IPC: G05F1/10
- IPC: G05F1/10

Abstract:
A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero.
Public/Granted literature
- US20110102045A1 INTERFACING BETWEEN DIFFERING VOLTAGE LEVEL REQUIREMENTS IN AN INTEGRATED CIRCUIT SYSTEM Public/Granted day:2011-05-05
Information query
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