A circuit arrangement is formed as follows. A combinational circuit has n binary inputs E1, . . . , En for inputting n (n≧2) information bits x1, . . . , xn and m binary outputs for outputting m (m≧1) check bits c1, . . . , cm. The combinational circuit is configured for realizing a Boolean function ci=fi(xi1, . . . , xini) for i=1, . . . , m at the i-th output for determining a check bit ci, wherein the set {xi1, . . . , xini} at the ni information bits that determine the check bit ci is a subset of all n information bits {x1, . . . , xn}. The combinational circuit is furthermore configured for realizing a first Boolean function f1(x11, . . . , x1n1) of the form c1=f1(x11, . . . , x1n1)=f11(x11, x12) XOR f12(x13, x14) XOR . . . XOR f1k1(x1(n1−1), x1n1) at a first output for outputting a first check bit c1, wherein n1 is an even number where n1≧2 and 2 k1=n1 and the Boolean functions f11(x11, x12), . . . , f1k1(x1(n1−1), x1n1) are in each case nonlinear Boolean functions of two variables which can be realized by logic gates having two inputs and one output, wherein the logic gates each have a controlling value c11, . . . , c1k1.