Invention Grant
US08138524B2 Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby
有权
形成具有源侧擦除的浮动存储单元的半导体存储器阵列的自对准方法，以及由此制成的存储器阵列
- Patent Title: Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby
- Patent Title (中): 形成具有源侧擦除的浮动存储单元的半导体存储器阵列的自对准方法，以及由此制成的存储器阵列
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Application No.: US11592104Application Date: 2006-11-01
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Publication No.: US08138524B2Publication Date: 2012-03-20
- Inventor: Alexander Kotov , Amitay Levi , Hung Q. Nguyen , Pavel Klinger
- Applicant: Alexander Kotov , Amitay Levi , Hung Q. Nguyen , Pavel Klinger
- Applicant Address: US CA Sunnyvale
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: DLA Piper LLP (US)
- Main IPC: H01L29/788
- IPC: H01L29/788
Abstract:
A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to the source, and a floating gate having a first portion disposed over and insulated from the source region and a second portion disposed over and insulated from the channel region. The floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge. An electrically conductive control gate is disposed over and insulated from the channel region for controlling a conductivity thereof.
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