Invention Grant
- Patent Title: Optimal bus operation performance in a logic simulation environment
- Patent Title (中): 逻辑仿真环境中最优总线运算性能
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Application No.: US12228587Application Date: 2008-08-14
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Publication No.: US08140314B2Publication Date: 2012-03-20
- Inventor: Robert J. Devins , David W. Milton
- Applicant: Robert J. Devins , David W. Milton
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent Richard Kotulak
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.
Public/Granted literature
- US20080312896A1 Optimal bus operation performance in a logic simulation environment Public/Granted day:2008-12-18
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