发明授权
- 专利标题： Serial bus clock frequency calibration system and method thereof
- 专利标题（中）： 串行总线时钟频率校准系统及其方法
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申请号： US12388373申请日： 2009-02-18
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公开(公告)号： US08140882B2公开(公告)日： 2012-03-20
- 发明人: Wei-te Lee , Shin-te Yang , Yen-fah Chu
- 申请人： Wei-te Lee , Shin-te Yang , Yen-fah Chu
- 申请人地址： TW Taipei
- 专利权人： Genesys Logic, Inc.
- 当前专利权人： Genesys Logic, Inc.
- 当前专利权人地址： TW Taipei
- 代理机构： Kirton McConkie
- 代理商 Evan R. Witt
- 优先权： TW97143548A 20081111
- 主分类号： H03D3/24
- IPC分类号： H03D3/24
摘要：
A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.