A multilayer ceramic electronic component includes a laminate including a stack of a plurality of ceramic layers and a plurality of internal electrodes extending along interfaces between the ceramic layers, and a plurality of external electrodes electrically connecting the internal electrodes exposed at surfaces of the laminate. Each external electrode includes a plating layer at least at the portion directly connected to the internal electrodes. The plating layer has a compressive film stress of about 100 MPa or less or a tensile film stress of about 100 MPa or less.