A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.