发明授权
- 专利标题： Semiconductor device fabrication method and semiconductor device
- 专利标题（中）： 半导体器件制造方法和半导体器件
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申请号： US11643907申请日： 2006-12-22
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公开(公告)号： US08163611B2公开(公告)日： 2012-04-24
- 发明人: Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
- 申请人： Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权： JPP2001-095038 20010329; JPP2001-123632 20010420; JPP2001-123633 20010420; JPP2002-047944 20020225
- 主分类号： H01L21/8249
- IPC分类号： H01L21/8249
摘要：
A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
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