Invention Grant
- Patent Title: Integrated semiconductor outline package
- Patent Title (中): 集成半导体外形封装
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Application No.: US12513906Application Date: 2006-12-05
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Publication No.: US08169069B2Publication Date: 2012-05-01
- Inventor: Stanley Job Doraisamy , Wae Chet Yong
- Applicant: Stanley Job Doraisamy , Wae Chet Yong
- Applicant Address: DE Munich
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Munich
- Agency: Slater & Matsil, L.L.P.
- International Application: PCT/SG2006/000379 WO 20061205
- International Announcement: WO2008/069755 WO 20080612
- Main IPC: H01L21/302
- IPC: H01L21/302

Abstract:
A transistor outline package is provided for a semiconductor integrated device suitable for use in a control module of an automobile for connection between a printed circuit board and a bus bar of such a module. The package includes a package housing, having a first end suitable for mounting to a PCB and which has a width. The package is also formed with a leadframe which includes a heat sink and ground plane blade suitable for connection to a bus bar, a plurality of connector leads suitable for connection to a PCB and at least one source tab lead suitable for connection to a module connector of such a control module. The plurality of connection leads and the source tab lead extend from the first end of the package housing side by side in the direction along and within the width of the first end of the package housing.
Public/Granted literature
- US20100007006A1 Integrated Semiconductor Outline Package Public/Granted day:2010-01-14
Information query
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