Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor (21) is in an off state during loading and writing and is in an on state during reading. An NMOS transistor (22) is turned on when a high level input is received and turned off when a low level input is received. An NMOS transistor (23) is in the off state during loading and writing and is in the on state during reading. A PMOS transistor (26) is in the on state during loading and is in the off state during writing and reading. A PMOS transistor (27) is turned off when the high level input is received during loading, is turned on when the low level input is received during loading, and is in the on state during writing and reading.