Invention Grant
US08179732B2 Flash memory devices including ready/busy control circuits and methods of testing the same 有权
闪存设备包括就绪/繁忙的控制电路和测试方法

Flash memory devices including ready/busy control circuits and methods of testing the same
Abstract:
A flash memory device includes a chip disable fuse circuit that has a fuse and that outputs a chip disable signal when the fuse is cut out, and a ready/busy control circuit that forcibly activates a ready/busy signal representing an internal operational state in response to the chip disable signal and externally outputs the ready/busy signal through a ready/busy output pin.
Information query
Patent Agency Ranking
0/0