Invention Grant
- Patent Title: Method of fabricating stacked semiconductor structure
- Patent Title (中): 叠层半导体结构的制造方法
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Application No.: US12829704Application Date: 2010-07-02
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Publication No.: US08183092B2Publication Date: 2012-05-22
- Inventor: Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
- Applicant: Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
- Applicant Address: TW Taichung
- Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee Address: TW Taichung
- Agency: Edward Wildman Palmer LLP
- Agent Peter F. Corless; Steven M. Jensen
- Priority: TW95103695A 20060203
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/46

Abstract:
A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.
Public/Granted literature
- US20100267202A1 METHOD OF FABRICATING STACKED SEMICONDUCTOR STRUCTURE Public/Granted day:2010-10-21
Information query
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