Invention Grant
US08183126B2 Patterning embedded control lines for vertically stacked semiconductor elements
有权
为垂直堆叠的半导体元件绘制嵌入式控制线
- Patent Title: Patterning embedded control lines for vertically stacked semiconductor elements
- Patent Title (中): 为垂直堆叠的半导体元件绘制嵌入式控制线
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Application No.: US12502178Application Date: 2009-07-13
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Publication No.: US08183126B2Publication Date: 2012-05-22
- Inventor: Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
- Applicant: Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
- Applicant Address: US CA Scotts Valley
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Scotts Valley
- Agency: Mueting, Raasch & Gebhardt PA
- Main IPC: H01L21/30
- IPC: H01L21/30

Abstract:
Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
Public/Granted literature
- US20110006377A1 Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements Public/Granted day:2011-01-13
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