Invention Grant
US08183911B2 High voltage tolerance of external pad connected MOS in power-off mode 有权
电源关闭模式下外部焊盘连接MOS的高电压容差

High voltage tolerance of external pad connected MOS in power-off mode
Abstract:
An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads.
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