Invention Grant
US08183911B2 High voltage tolerance of external pad connected MOS in power-off mode
有权
电源关闭模式下外部焊盘连接MOS的高电压容差
- Patent Title: High voltage tolerance of external pad connected MOS in power-off mode
- Patent Title (中): 电源关闭模式下外部焊盘连接MOS的高电压容差
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Application No.: US12581578Application Date: 2009-10-19
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Publication No.: US08183911B2Publication Date: 2012-05-22
- Inventor: Somnath Kundu , Pikul Sarkar , Nitin Gupta
- Applicant: Somnath Kundu , Pikul Sarkar , Nitin Gupta
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Gardere Wynne Sewell LLP
- Main IPC: G11C5/14
- IPC: G11C5/14

Abstract:
An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads.
Public/Granted literature
- US20110090002A1 HIGH VOLTAGE TOLERANCE OF EXTERNAL PAD CONNECTED MOS IN POWER-OFF MODE Public/Granted day:2011-04-21
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