发明授权
- 专利标题: Method for data processing using a multi-tiered full-graph interconnect architecture
- 专利标题(中): 使用多层全图互连架构进行数据处理的方法
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申请号: US11845207申请日: 2007-08-27
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公开(公告)号: US08185896B2公开(公告)日: 2012-05-22
- 发明人: Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
- 申请人: Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Francis Lammes; Stephen J. Walder, Jr.; Diana R. Gerhardt
- 主分类号: G06F9/46
- IPC分类号: G06F9/46
摘要:
A method is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.
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