A voltage memory stores a signal level of a transmission signal from a signal generator at a timing of a clock signal, and outputs the transmission signal. A voltage difference detector detects a signal level of a transmission signal at a timing subsequent to the timing and detects a first signal level difference between the signal level and the signal level from the voltage memory. A maximum value detector, a voltage difference detector and bias voltage sources delay the transmission signal so as to keep a rise time of the transmission signal substantially within a predetermined value range by adding capacitances corresponding to the first signal level differences from the voltage difference detectors to transmission lines.