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US08194855B2 Method and apparatus for implementing processor instructions for accelerating public-key cryptography 有权
用于实现用于加速公钥密码术的处理器指令的方法和装置

Method and apparatus for implementing processor instructions for accelerating public-key cryptography
摘要：
In response to executing a single arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is added implicitly to generate a result that represents the first number multiplied by the second number summed with the partial result from a previously executed single arithmetic instruction. The high order portion of the generated result is saved in an extended carry register as a next partial result for use with execution of a subsequent single arithmetic instruction. Execution of a single arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number.
摘要（中）：

响应于执行单个算术指令，将第一数乘以第二数，并且隐式地添加来自先前执行的单个算术指令的部分结果，以生成表示第一数乘以与第二数相乘的第二数的结果 来自先前执行的单个算术指令的部分结果。 生成结果的高阶部分作为下一个部分结果保存在扩展进位寄存器中，用于执行后续的单个算术指令。 可以执行单个算术指令来产生表示第一个数乘以与部分结果相加的第二个数字并且与第三个数字相加的结果。

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