The transmission side device 10 is provided with a memory MT for holding a plurality of transmission signals transmitted last time and the reception side device 20 is provided with a memory MR for holding a plurality of reception signals received last time, thereby checking existence/non-existence of a change of a transmission signal to be transmitted this time by a comparator C. The transmission unit 103 transmits the changed part signal SL for discriminating a changed signal and the change end signal SE. The reception side device 20 equivalently receives a transmission signal as of this time by detecting and changing a changed signal among signals held in the memory MR based on the changed part signal SL. The clock generation unit 30 changes the circuit operation clock CLKC to advance the transmission circuit 101 and the reception circuit 201 by one cycle by receiving the change end signal SE. This enables data transmission/reception between devices to be sped up, as well as enabling high-speed operation of the entire system.