发明授权
- 专利标题: Early estimation of power consumption for electronic circuit designs
- 专利标题(中): 电子电路设计功耗的早期估计
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申请号: US12128602申请日: 2008-05-28
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公开(公告)号: US08201121B1公开(公告)日: 2012-06-12
- 发明人: Ranganathan P. Sankaralingam , Yan Meng
- 申请人: Ranganathan P. Sankaralingam , Yan Meng
- 申请人地址: US CA San Jose
- 专利权人: Cadence Design Systems, Inc.
- 当前专利权人: Cadence Design Systems, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Alford Law Group, Inc.
- 代理商 William E. Alford
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
In one embodiment of the invention, a method of designing integrated circuits is disclosed. The method includes determining a power correction factor for a subset of partitions of circuits in an integrated circuit design; determining a gross power consumption estimate for all partitions of circuits in the integrated circuit design without synthesizing the entire integrated circuit design; and improving the accuracy of the gross power consumption estimate using the power correction factor to generate a reasonably accurate power consumption estimate for the entire integrated circuit design prior to substantially full circuit synthesis thereof.
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