Provided is a technology capable of managing the processing status of hardware blocks by a less number of registers. A processing system includes a buffer composed of a plurality of segments which store data, which is to be input to the processing system, in transactions in the order of inputting, respectively; a plurality of processing units which perform a series of processes in a given order for the data; a plurality of first tables corresponding to the plurality of processing units, respectively, the first tables each storing beginning information which indicates a beginning segment among a plurality of segments at continuous addresses completed in the process by the corresponding processing unit, end information which indicates an end segment among them, and existence information which indicates the presence or absence of segments completed in the process by the corresponding processing unit; and a management unit which manages a data transfer between the buffer and the plurality of processing units so that the series of processes are performed in a given order on the basis of the processing status of the series of processes retained in the plurality of first tables.