发明授权
US08212353B1 Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate
有权
针对低K Si和薄芯基板设计的低应力薄晶片倒装芯片封装的结构和组装程序
- 专利标题： Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate
- 专利标题（中）： 针对低K Si和薄芯基板设计的低应力薄晶片倒装芯片封装的结构和组装程序
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申请号： US12778905申请日： 2010-05-12
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公开(公告)号： US08212353B1公开(公告)日： 2012-07-03
- 发明人: Wen-chou Vincent Wang , Yuan Li , Bruce Euzent , Vadali Mahadev
- 申请人： Wen-chou Vincent Wang , Yuan Li , Bruce Euzent , Vadali Mahadev
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Weaver Austin Villeneuve & Sampson LLP
- 主分类号： H01L23/34
- IPC分类号： H01L23/34
摘要：
Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.
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