发明授权
- 专利标题: Memory access system
- 专利标题(中): 内存访问系统
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申请号: US12170102申请日: 2008-07-09
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公开(公告)号: US08214725B2公开(公告)日: 2012-07-03
- 发明人: Takahiko Sugahara
- 申请人: Takahiko Sugahara
- 申请人地址: JP Osaka-shi
- 专利权人: MegaChips Corporation
- 当前专利权人: MegaChips Corporation
- 当前专利权人地址: JP Osaka-shi
- 代理机构: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- 优先权: JP2007-205651 20070807
- 主分类号: H03M13/00
- IPC分类号: H03M13/00
摘要:
The Error Correction Code (ECC) circuit generates the first syndrome of write data, which have not been written to the memory. The Error Detection Code (EDC) circuit generates the second syndrome of verification read data, which have been written to the memory. The EDC circuit detects errors due only to the “read disturb phenomenon” using the second syndrome, the errors occurring in data scanned from the memory. The ECC circuit detects and corrects errors due to the “program disturb phenomenon” and the “read disturb phenomenon” using the first syndrome, the errors occurring in the data in which the errors due only to the “read disturb phenomenon” have been detected. As a result, both the circuit size and the processing time can be reduced.
公开/授权文献
- US20090044076A1 MEMORY ACCESS SYSTEM 公开/授权日:2009-02-12
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