发明授权
US08222967B1 Receiver equalizer circuitry having wide data rate and input common mode voltage ranges
有权
接收机均衡器电路具有宽数据速率和输入共模电压范围
- 专利标题: Receiver equalizer circuitry having wide data rate and input common mode voltage ranges
- 专利标题(中): 接收机均衡器电路具有宽数据速率和输入共模电压范围
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申请号: US12644128申请日: 2009-12-22
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公开(公告)号: US08222967B1公开(公告)日: 2012-07-17
- 发明人: Sangeeta Raman , Tim Tri Hoang , Sergey Yuryevich Shumarayev
- 申请人: Sangeeta Raman , Tim Tri Hoang , Sergey Yuryevich Shumarayev
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Ropes & Gray LLP
- 主分类号: H03H7/30
- IPC分类号: H03H7/30 ; H03F3/45
摘要:
Equalizer circuitry on an integrated circuit (“IC”) includes a plurality of NMOS equalizer stages connected in series. Each NMOS stage may include folded active inductor circuitry. Each NMOS stage may also include various circuit elements having controllably variable circuit parameters so that the equalizer can be controllably adapted to perform for any of a wide range of high-speed serial data signal bit rates and other variations of communication protocols and/or communication conditions. For example, each NMOS stage may be programmable to control at least one of bandwidth and power consumption of the equalizer circuitry. The equalizer may also have a first PMOS stage that can be used instead of the first NMOS stage in cases in which the voltage of the incoming signal to be equalized is too low for an initial NMOS stage.