发明授权
US08227295B2 IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
有权
具有TSV和晶片级底部填充的IC芯片和包括连接到TSV的工件焊料的堆叠IC器件
- 专利标题： IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
- 专利标题（中）： 具有TSV和晶片级底部填充的IC芯片和包括连接到TSV的工件焊料的堆叠IC器件
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申请号： US12416694申请日： 2009-04-01
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公开(公告)号： US08227295B2公开(公告)日： 2012-07-24
- 发明人: Margaret R. Simmons-Matthews , Donald C. Abbott
- 申请人： Margaret R. Simmons-Matthews , Donald C. Abbott
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Steven A. Shaw; W. James Brady; Frederick J. Telecky, Jr.
- 主分类号： H01L21/00
- IPC分类号： H01L21/00
摘要：
A method of forming integrated circuit (IC) die configured for attachment to another die or a package substrate, and stacked IC devices therefrom. At least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip.
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