Method of fabricating a transistor with semiconductor gate combined locally with a metal

Invention Grant

US08227342B2 Method of fabricating a transistor with semiconductor gate combined locally with a metal 有权

Title translation: 制造具有与金属局部组合的半导体栅极的晶体管的方法

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Patent Title: Method of fabricating a transistor with semiconductor gate combined locally with a metal
Patent Title (中): 制造具有与金属局部组合的半导体栅极的晶体管的方法
Application No.: US12521802

Application Date: 2008-01-10
Publication No.: US08227342B2

Publication Date: 2012-07-24
Inventor: Markus Müller , Grógory Bidal
Applicant: Markus Müller , Grógory Bidal
Applicant Address: FR Crolles NL Ag Eindhoven
Assignee: STMicroelectronics (Crolles 2) SAS,NXP B.V. (Dutch Corporation)
Current Assignee: STMicroelectronics (Crolles 2) SAS,NXP B.V. (Dutch Corporation)
Current Assignee Address: FR Crolles NL Ag Eindhoven
Agency: Wolf, Greenfield & Sacks, P.C.
Priority: EP07300721 20070111
International Application: PCT/EP2008/050260 WO 20080110
International Announcement: WO2008/084085 WO 20080717
Main IPC: H01L21/8234
IPC: H01L21/8234

Method of fabricating a transistor with semiconductor gate combined locally with a metal

Abstract:

A method of forming a field effect transistor comprising a gate formed on an insulating layer, the gate having, in a zone in contact with the insulating layer, a semiconducting central zone and lateral zones in the length of the gate, the method comprising forming a gate comprising a portion of insulating layer, a portion of semiconducting layer formed over the insulating layer, and a portion of mask layer formed over the semiconducting layer; performing an etching of the portion of the mask layer such that only a portion in the center of the gate remains; and reacting the semiconducting gate with a metal deposited over the gate.

Abstract(Chinese):

一种形成场效应晶体管的方法，所述场效应晶体管包括形成在绝缘层上的栅极，所述栅极在与所述绝缘层接触的区域中具有在所述栅极长度上的半导体中心区域和侧向区域，所述方法包括形成包括绝缘层的一部分的栅极，在绝缘层上形成的半导体层的一部分，以及形成在半导体层上的掩模层的一部分; 对所述掩模层的所述部分进行蚀刻，使得只有所述栅极的中心部分保留; 并使半导电栅极与沉积在栅极上的金属反应。

Public/Granted literature

US20100102402A1 METHOD OF FABRICATING A TRANSISTOR WITH SEMICONDUCTOR GATE COMBINED LOCALLY WITH A METAL Public/Granted day:2010-04-29

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺