A method for fabricating integrated circuit (ICs) having through substrate vias (TSVs) includes forming active circuit elements on a semiconductor wafer and then forming a plurality of embedded vias through the top side of the wafer. A metal filler layer including a filler metal is deposited to fill the embedded vias. Chemical mechanical polishing (CMP) then forms a plurality of embedded TSVs that have polished top TSV surfaces having exposed filler metal. An electrically conductive hillock suppression structure is formed by forming a silicon or germanium doped region, or a silicide or germanicide at the polished top TSV surface or by forming a metal layer on the polished top TSV surface having a composition different from the filler metal. A dielectric layer is deposited on the semiconductor wafer including over the hillock suppression structure. The dielectric layer is removed over the polished top TSV surface to allow metal contact thereto.