发明授权
US08227916B2 Package structure and method for reducing dielectric layer delamination 有权
用于减少介电层分层的封装结构和方法

Package structure and method for reducing dielectric layer delamination
摘要:
A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.
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